A current common requirement for an advanced electronic circuit and particularly for circuits manufactured as integrated circuits (“ICs”) in semiconductor processes is the use of multiple integrated circuit devices (“dies”) in a single packaged component. Typical arrangements include so-called “flip chip” packages where integrated circuit dies are mounted to an interposer using solder bumps or solder columns. The solder bumps may include lead based or more recently lead free materials such as eutectics. Once the dies are mounted onto the interposer a thermal reflow step is often performed to complete the mechanical and electrical connection to the die side surface of the interposer by melting the solder balls or bumps to cause them to bond to the pads on the die side of the interposer, and then allowing them to cool, or reflow. The resulting solder connection is a mechanical attachment and an electrical connection between the bond pads on the integrated circuit, which are coupled to devices within the integrated circuit, and the redistribution layer (“RDL) or conductors within the interposer. Often the opposing side of the interposer will receive solder balls, which are larger than but similar to the solder bumps, to form a “ball grid array” or BGA package. As the number and complexity of the dies mounted in such a package increase, the multi-chip package now sometimes replaces what was a board or system, and the completed device may be referred to as a “SoC”, or “system on a chip”.
Applications for such multiple chip packages are numerous. Because certain types of dedicated devices are commonly used, it is often needed to put these devices together to complete a functional design for a particular use. Combining microprocessor devices with program memory storage such as FLASH or EEPROM devices, combining microprocessors with application specific processors such as baseband transceivers, graphics processors, cache memory devices, memory management devices, and analog to digital converters for sensor applications, are all useful and commonly used arrangements that provide applications for the structures described herein.
After the dies are mounted to the interposer, an underfill material is typically dispensed around and underneath the dies. This underfill provides a stress relief, and in particular provides thermal stress relief for the solder balls. Since there is a thermal mismatch between the integrated circuit devices and the interposer the solder balls can be damaged by the physical stresses that occur due to the thermal expansion of the devices while in operation. The underfill provides a flexible compliant material surrounding the solder balls and between the dies and the surface of the interposer, and helps prevent solder ball failures dues to these stresses, or even die cracking that might otherwise occur.
In some arrangements, a mold compound structure is formed over the dies after the underfill is formed. The underfill “fillet”, which is the area of underfill material that forms at the die edge and extends outside the die footprint and has an outside surface that slopes up to the die bottom surface, is then encapsulated in mold compound material. If there are voids in the mold compound or the two materials are not completely continuous, then additional areas for possible thermal stress problems are formed at the interface of these materials.
Dispensing the underfill in a prior art package using flip chip devices is difficult. The space between the dies is particularly hard to fill with an underfill dispensed after the bare dies are mounted to the interposer. Often voids remain, particularly in the spaced between the dies. These voids may lead to failures later and must be avoided.
A continuing need for interposer based packages and methods for multiple chip packages for flip chip integrated circuits that reduce or eliminate the problems associated with the prior art assemblies and methods thus exists.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.